Field of Invention
The present invention relates to a display apparatus. Particularly it relates to a display apparatus with fewer signal lines. The present invention also relates to a gate-driver on array (GOA) control circuit for use in the display apparatus.
Description of Related Art
FIG. 1 shows a prior art display apparatus (display apparatus 1) disclosed in U.S. Pat. No. 9,595,219B2, wherein a timing controller (Tcon) 110 controls a level shifter 130 to generate scanning management signals (such as CLK, VST, VRST shown in the figure) which control the GOA 140 to generate the gate driving signal GL for controlling the vertical scanning operation of the display panel unit 100A. The display panel 100 includes plural display panel units (such as 100A) which are arranged in a two dimensional array with plural rows and plural columns. The aforementioned vertical scanning operation indicates that the rows of the display panel 100 are sequentially selected along the vertical direction.
The prior art circuit in FIG. 1 has a drawback that the output signals of the timing controller 110 substantially are in a one-to-one relationship with the scanning management signals. Therefore, the total number of the signal lines between the timing controller 110 and the level shifter 130 is enormously large in high resolution display panel applications, which leads to high cost and design difficulty. Besides, such kind of display apparatus architecture is usually dedicated for display panels of one single model which has one set of predetermined panel parameters. Such architecture is not applicable to display panels of different models with various different panel parameters.
Compared to the prior art in FIG. 1, the present invention is advantageous in higher flexibility which can support various models of display panels and in lower overall cost of the display apparatus.
Relevant prior patents are U.S. Pat. Nos. 9,595,219B2, 7,471,286B2 and 9,013,468B2, which solve the issue by different approaches from the present invention.